Computer systems are increasingly being designed using microprocessors with a number of processing cores (“multi-core processor”) therein. A “core” is defined in this disclosure as an integrated circuit having at least one execution unit to execute to instructions, including, but not limited to, an arithmetic logic unit (ALU). In some multi-core processors, each core may be integrated with or may otherwise use a local cache memory to store data and/or instructions specific to a particular core. In order to maintain coherency between the local caches as well as other caches within the processor or computer system that may be accessed by the cores, logic may be associated with each local cache that implements a coherency protocol (“protocol engine”).
In some multi-core processors, each processor core has an associated protocol engine to maintain coherency between the processor's local cache and other caches. However, in other multi-core processors, one protocol engine, or at least fewer protocol engines than the number of cores, is/are used to maintain coherency among all of the local caches and/or other caches within the processor or outside of the processor that may be accessed by the cores. In the latter case, information is typically communicated among the cores (“cache agents”) or to devices (“agents”) outside of the multi-core processor across an interconnect (“processor interconnect”) via the protocol engine.
FIG. 1 illustrates a prior art arrangement of cache agents within a multi-core processor that communicate via a centralized protocol agent that maintains coherency among the cache agents. In the arrangement illustrated in FIG. 1, caching transactions, such as data and/or cache ownership requests, data write-back operations, and other cache probe operations and responses are sent on rings 112 and 114 (“address” rings) and transactions, such as cache fill acknowledgements and cache probe responses, such as a cache “hit” or “miss” indication, are transmitted on rings 111 and 113 (“non-address” rings). In other arrangements the above or other transactional information may be transmitted on other combinations of the rings 111-114. Each set of cache agents communicates information between each other via protocol engine 110, which maintains cache coherency among the cache agents.
In some computer systems, especially those having a number of microprocessors (multi-core or single-core), the devices (“agents”) within the computer system typically communicate via an interconnect (“system interconnect”) according to a certain set of commands, rules, or protocol. For example, a point-to-point (P2P) computer system, in which no more than two agents share an interconnect, or “link”, messages may be communicated among agents according to a common set of rules and control information. Typically, the same rules and control information used to communicate information among a number of agents within a P2P computer system are the same as those used to deliver information to or transmit information from cores of any multi-core processors within the P2P computer system.
Using the same communication rules and control information to communicate between agents on a system interconnect to/from cores on a processor interconnect can require the protocol engine or some other logic within, or otherwise associated with a multi-core processor, to implement the same communication rules and control information as the agents on the system interconnect. In some cases, this may require extra logic and may impede the efficiency of communication between the protocol engine and the various cores.
This may be particularly true if two or more communication rules or control information used to communication information on the system interconnect have the same effect on a core or cores on a processor interconnect. In this case, it may less-than-optimal, in terms communication cycles and/or logic, to communicate the information from the system interconnect to the processor interconnect using the same two or more communication information or rules to communicate from the system interconnect to a core or cores on the processor interconnect.